1. Field of the Invention
The present invention relates to a Viterbi decoder for use in a mobile communication system and the like to decode a convolutional code by a Viterbi decoding system for conducting maximum likelihood decoding based on Viterbi algorithms.
2. Description of the Related Art
One of common decoding systems for decoding a convolutional code is the Viterbi decoding system which conducts maximum likelihood decoding based on Viterbi algorithms. A Viterbi decoder for decoding a convolutional code according to the Viterbi decoding system is employed in a mobile communication system and the like because of its high capability in correcting random errors caused on a communication line in a communication system.
A Viterbi decoder conducts, with respect to applied data, ACS processing (addition, comparison, selection) of adding branch metrics output from a branch metric generation means and path metrics read from a path metric memory means, comparing them and selecting a smaller one, stores path metric data in the path metric memory means and stores selection information on a remaining path of the ACS processing in a path memory.
Since a conventional Viterbi decoder has only one system of a branch metric generation means and a means for conducting ACS processing, at the decoding of applied data, the above-described processing should be executed as many times as the number of states.
Also, because path metric data should be read from a path metric memory means twice at the time of the ACS processing, a conventional Viterbi decoder conducts reading of path metric data from one path metric memory in two times for one ACS processing.
As described above, since a conventional Viterbi decoder has only one system of the branch metric generation means and the means for conducting ACS processing, the decoder should conduct the above-described processing as many times as the number of states at the time of decoding applied data, requiring enormous time for the processing.
Another shortcoming is that since a conventional Viterbi decoder conducts reading of path metric data from one path metric memory in two times for one ACS processing, one ACS processing at the minimum needs a time of reading path metric data twice from the path metric memory means, which makes more speed-up impossible.
An object of the present invention is to overcome the above-described conventional shortcomings and provide a Viterbi decoder which enables speed-up of processing by multiplexing generation of a branch metric and ACS processing, as well as reducing the number of times of reading of path metric data from a path metric memory at the time of the ACS processing.
According to one aspect of the invention, a Viterbi decoder for conducting maximum likelihood decoding of a convolutional code based on Viterbi algorithms, comprises
branch metric generation means for generating a branch metric based on input data,
ACS execution means for conducting ACS processing using the branch metric generated by the branch metric generation means,
path memory means for storing a path selected by the ACS processing,
path metric holding means for storing new path metric data generated by the ACS processing and returning the new data again to the ACS execution means,
address generation means for conducting generation of a memory address and memory switching control in the path metric holding means, and
number of states counter means for instructing the branch metric generation means and the address generation means on a processing cycle, wherein
the branch metric generation means executes the branch metric generation processing in multiplexing, and
the ACS execution means executes the ACS processing in a multiplicity corresponding to the branch metric generation processing.
In the preferred construction, the path metric holding means comprises two systems of memories for storing the path metric data, and writes the path metric data output from the ACS execution means divisionally to the two systems of memories, as well as reading the path metric data from the two systems of memories to distribute and output to the ACS execution means.
In another preferred construction, the path metric holding means comprises two systems of memories for storing the path metric data, first switching means for writing the path metric data output from the ACS execution means divisionally to the two systems of memories, and second switching means for reading the path metric data from the two systems of memories to distribute and output to the ACS execution means.
In another preferred construction, the ACS execution means comprises as many ACS blocks as the number corresponding to the multiplicity which execute ACS processing of adding the branch metrics received from the branch metric generation means and the path metric data read from the path metric holding means, comparing addition results and selecting a smaller path.
In another preferred construction, the ACS execution means comprises as many ACS blocks as the number corresponding to the multiplicity which execute ACS processing of adding the branch metrics received from the branch metric generation means and the path metric data read from the path metric holding means, comparing addition results and selecting a smaller path, and
the path metric holding means comprises two systems of memories for storing the path metric data, writes the path metric data output from the ACS execution means divisionally to the two systems of memories, and reads the path metric data from the two systems of memories to distribute to the ACS blocks of the ACS execution means.
In another preferred construction, the ACS execution means comprises as many ACS blocks as the number corresponding to the multiplicity which execute ACS processing of adding the branch metrics received from the branch metric generation means and the path metric data read from the path metric holding means, comparing addition results and selecting a smaller path, and
the path metric holding means comprises two systems of memories for storing the path metric data, first switching means for writing the path metric data output from the ACS execution means divisionally to the two systems of memories, and second switching means for reading the path metric data from the two systems of memories to distribute to the ACS blocks of the ACS execution means.
In another preferred construction, the ACS execution means comprises, as many as the number corresponding to the multiplicity, addition means for adding the branch metrics received from the branch metric generation means and the path metric data read from the path metric holding means, and comparison and selection means for comparing addition results obtained by the addition means to select a smaller path,
the addition means and the comparison and selection means executing processing in parallel to each other.
In another preferred construction, the ACS execution means comprises, as many as the number corresponding to the multiplicity, addition means for adding the branch metrics received from the branch metric generation means and the path metric data read from the path metric holding means, and comparison and selection means for comparing addition results obtained by the addition means to select a smaller path,
the addition means and the comparison and selection means executing processing in parallel to each other, and
the path metric holding means comprises two systems of memories for storing the path metric data, first switching means for writing the path metric data output from the ACS execution means divisionally to the two systems of memories, and second switching means for reading the path metric data from the two systems of memories to distribute to the addition means of the ACS execution means.
According to another aspect of the invention, a Viterbi decoder for conducting maximum likelihood decoding of a convolutional code based on Viterbi algorithms, comprises
a branch metric generation circuit for generating a branch metric based on input data,
an ACS execution circuit for conducting ACS processing using the branch metric generated by the branch metric generation circuit,
a path memory for storing a path selected by the ACS processing,
a path metric holding circuit for storing new path metric data generated by the ACS processing and returning the new data again to the ACS execution circuit,
an address generation circuit for conducting generation of a memory address and memory switching control in the path metric holding circuit, and
a number of states counter for instructing the branch metric generation circuit and the address generation circuit on a processing cycle, wherein
the branch metric generation circuit executes the branch metric generation processing in multiplexing, and
the ACS execution circuit executes the ACS processing in a multiplicity corresponding to the branch metric generation processing.
In the preferred construction, the path metric holding circuit comprises two systems of memories for storing the path metric data, a first switch for writing the path metric data output from the ACS execution circuit divisionally to the two systems of memories, and a second switch for reading the path metric data from the two systems of memories to distribute and output to the ACS execution circuit.
In another preferred construction, the ACS execution circuit comprises as many ACS blocks as the number corresponding to the multiplicity which execute ACS processing of adding the branch metrics received from the branch metric generation circuit and the path metric data read from the path metric holding circuit, comparing addition results and selecting a smaller path.
In another preferred construction, the ACS execution circuit comprises as many ACS blocks as the number corresponding to the multiplicity which execute ACS processing of adding the branch metrics received from the branch metric generation circuit and the path metric data read from the path metric holding circuit, comparing addition results and selecting a smaller path, and
the path metric holding circuit comprises two systems of memories for storing the path metric data, a first switch for writing the path metric data output from the ACS execution circuit divisionally to the two systems of memories, and a second switch for reading the path metric data from the two systems of memories to distribute to the ACS blocks of the ACS execution circuit.
In another preferred construction, the ACS execution circuit comprises, as many as the number corresponding to the multiplicity, an addition circuit for adding the branch metrics received from the branch metric generation circuit and the path metric data read from the path metric holding circuit, and a comparison and selection circuit for comparing addition results obtained by the addition circuit to select a smaller path,
the addition circuit and the comparison and selection circuit executing processing in parallel to each other.
In another preferred construction, the ACS execution circuit comprises, as many as the number corresponding to the multiplicity, an addition circuit for adding the branch metrics received from the branch metric generation circuit and the path metric data read from the path metric holding circuit, and a comparison and selection circuit for comparing addition results obtained by the addition circuit to select a smaller path,
the addition circuit and the comparison and selection circuit executing processing in parallel to each other, and
the path metric holding circuit comprises two systems of memories for storing the path metric data, a first switch for writing the path metric data output from the ACS execution circuit divisionally to the two systems of memories, and a second switch for reading the path metric data from the two systems of memories to distribute to the addition circuit of the ACS execution circuit.
Other objects, features and advantages of the present invention will become clear from the detailed description given herebelow.